1. Field of the Invention
The embodiments of the invention generally relate to metal oxide semiconductor field effect transistor (MOSFET) devices, and, more particularly, to triple well technology in such MOSFET devices.
2. Description of the Related Art
Both noise isolation and the elimination of CMOS latchup are significant issues in advanced complementary metal oxide semiconductor (CMOS) technology and bipolar CMOS (BiCMOS) Silicon Germanium (SiGe) technology. More particularly, as MOSFET threshold voltages decrease, the need to isolate circuitry from noise sources becomes more important and has lead to an increased interest in “isolated MOSFETs” (i.e., triple well technology). In current triple well technology, a buried n-type layer (i.e., a buried n+ layer) is placed below the p-well and a buried p-type layer (i.e., a p+ layer) is placed below the n-well (or n-well/sub-collector combinations) at the same level, but not displaced. The buried n+ layer serves to isolate the p-well from the p− substrate. It was once believed that triple well technology would eliminate latchup. However, since in the process of isolating the p-well critical parameters that influence latchup robustness are modified, latchup remains a concern for the triple well technology in its current form. Additionally, because the buried n+ layer must overlap the n-wells in order to isolate the p-well, spacing issues present a problem in the current triple well CMOS formation process.